- Bit and work clock used in digital communication verification#
- Bit and work clock used in digital communication code#
- Bit and work clock used in digital communication series#
The output of crystal oscillator is transmitted into two clock signals with a duty ratio of about 1/4 and a phase difference of π, which are used together with the leading and lagging control pulses as input signals to the control module. The idea of DPLL method to extract bit synchronized clock is shown in Figure 1, which includes four main steps of crystal oscillator signal shaping, frequency division, phase detection, and control. The Principle of Bit Synchronization Clock Extraction Based on DPLL Local and global analysis can be done with reference to classic PLL-based circuit. In this paper we omit rigorous mathematical proof of local and global stability of proposed circuit. This implementation can be used to avoid the alternation of leading and lagging pulses after the synchronous locking and to improve the phase jitter problem caused by the random noise effect. The main idea is to implement a digital filter between the PD (Phase Detector) and the control module, which is used to process the leading or lagging control pulses corresponding to the phase difference of the PD output before sending them to the control module for a phase adjustment to its clock. This work is to present an improved DPLL based design for bit synchronized clock extraction in digital communication system. At present, the system that uses phase-locked loop to extract bit synchronous clock has complex extraction process, slow running speed, or lack of ability to resist random noise. The DPLL method is mature and widely used. In the self-synchronizing digital communication system, the methods to extract the bit synchronized signal mainly includes filtering method, enveloping “collapse” method, and DPLL (Digital Phase-Locked Loop) method.
Bit and work clock used in digital communication code#
The self-synchronization method extracts the synchronization information from the code in the receiving end without inserting the pilot signal at the transmitter end, making it the most commonly used method in modern digital communication. The process of extracting the timing pulse sequence is called bit synchronization, which is implemented by an external or a self-synchronization method.
Bit and work clock used in digital communication series#
In digital communication systems, information is transmitted in a series of code sequences the receiver must know the starting and ending time of each code, so it needs to have a bit timing pulse sequence for the sampling decision, which has the same repetition frequency as the code rate of transmit end and the same phase as the optimal decision time.
The results show that the improved system performs the accurate extraction of bit synchronized clock, reduces the phase jitter problem, improves the system running efficiency and the ability of anti-interference, and guarantees the synchronization performance of the digital communication system.
Bit and work clock used in digital communication verification#
The design is completed by using FPGA chip and VHDL hardware description language and performs the simulation verification on Quartus II. By using a newly added digital filter between the phase detector and the controller, the phase difference pulses from the phase detector are counted and processed, before being transmitted to the controller for adjusting the phase of the output clock. An improved method is proposed in this design to reduce the phase jitter after the synchronization or the random noise induced phase jitter in a bit synchronization clock extraction circuit.
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